I got stuck (again) while working on my 32-bit 80386DX ISA Single Board Microcomputer project. The issues that I am facing at the moment cannot be solved with an oscilloscope or a frequency counter. It is true that in the past, these two tools helped me debug the early design faults. But now I need way more hardware debugging capabilities. After a two weeks marathon of documentation reading and browsing the Internet, I decided to get myself one of the old boat anchors made by Hewlett-Packard throughout the 1990s decade. The alternative would have been a modern, small, and very expensive USB logic analyzer. I was thinking about the Saleae Logic Pro 16 model. But with only 16 channels and priced close to $ 1,000 ... it was an instant show-stopper. Thus I bought the Hewlett-Packard 16500C Logic Analysis System for a very small fraction of Saleae's price tag. In fact it was cheaper than one bare PCB for the 386DX project. Say what? It was just too good an offer to refuse.
As expected, the analyzer had problems. Parts of it were already defective and other sub-assemblies were about to fail. Which is entirely normal for a unit of this complexity and this age. In the end it turned out to be a side project on its own. But I fixed them all so now I can move along the line and prepare the machine for use according to my needs.
The 16500C logic analysis mainframe is a powerful tool for hardware debugging of multi parallel bus system designs. But without the right hardware and software configuration and operation knowledge, it is nothing more than a ... boat anchor. So the purpose of this essay is to document the steps that I did in order to bring this machine to life and adapt it to my needs.
This is not a tool that you can just power on and start using it. It is very complex and I imagine that back then there were trained people and workshops available for ramping up on digital microelectronics hardware debugging with the help of a logic analyzer. I don't know who was the main target of these machines. But I think mostly big companies developing cutting edge systems. Nowadays nobody wants these and individuals like you and me have a chance of buying one cheap and self-learn how to fix, maintain, operate, and interpret the results.
Logic analyzers are not generic tools that you have to have on your workbench. Unless you are designing digital microelectronics projects using parallel buses, these machines have little to no use. But if you need one to solve a complex digital timing problem, for instance, then it absolutely pays off.
Let the journey begin.
First of all I have gathered enough documentation on the machine and the adjacent installable cards.
Hewlett-Packard test and measurement equipment division was sold to Agilent which in turn was sold to Keysight. Thankfully the documentation and software are all still available for download, free of charges. I have downloaded the following documents from the Keysight site.
Some of the documents are very useful while the other ones are less useful for this essay. But still good to have around for references.
The hardware configuration of such a complex system can be split into individual system and acquisition configurations.
The system controller is a card of its own. It is the bottom-most card of them all and implements a complete computer that talks to the acquisition cards and interprets the results. It also controls the human interface devices (thumb-wheel and touch-screen), interfaces the hard disk drive and floppy disk drive, controls the PS/2 peripherals, the LAN interface, extension interfaces, and it drives the display.
This computer is equipped with standard memories under the form of 80 ns 72-pin EDO SIMMs. There are two SIMM sockets. My unit had a single 8 Mb module installed in Slot 0 (close to the back of the system card). Because I am going to use this mainframe intensively with extended analyzers, I decided to increase the RAM size to 32 Mb under the form of two 16 Mb RAM modules.
That's it for the system hardware configuration.
The 16500C mainframe has five expansion slots, each accepting a variety of compatible acquisition cards. These cards can be logic analyzers, digital sampling oscilloscopes, pattern generators, and possibly other.
I was lucky that my unit came with four individual HP 16555A 110 MHz state / 500 MHz timing logic analyzer cards. And some mismatched interconnection cables. These cards can be configured in a variety of master-extension ways. As it was configured, the mainframe would have been using one analyzer card as master, another one as extension, and the other two were configured as stand-alone master analyzers. This configuration is not very useful to me. So I thought about what I wanted from the machine and figured out the best would be to have the following.
So now there are two independent logic analyzers. One in Slot A with 64 acquisition channels and 2 clock channels. And the other one is in Slot B with 192 acquisition channels and 6 clock channels.
For simple simulations I will use the single logic analyzer in Slot A and for complex simulations such as the 386DX system, I will use the extended logic analyzer in slot D.
The software configuration of this mainframe can be split into several individual independent configurations.
The latest system software is also still available on the Keysight site. It is version 1.09 and it is dated 03/05/99. From my understanding, this version also fixes some issues with using 16533A and 16534A oscilloscope cards. Which is good news for DSO users.
There are two ways of getting the system software on the 16500C hard disk drive.
As you can see the system software comes with all the drivers for some very interesting cards that are probably hard to find.
I used the second method as it is the fastest. Though you need to configure the LAN interface first.
The main screen that is displayed after the system is booted up is the system configuration. Here you can quickly setup printer, controller, X-Window, RS-232, HP-IB, LAN, target control, and 16505A prototype analyzer settings. In addition you can see a brief configuration of the cards installed in the mainframe.
The following lines list the configuration of my machine.
By going to the [ System ] Utilities menu you can calibrate the touch-screen, adjust the real-time clock, enable or disable sounds, and switch colors. I just calibrated the touch-screen and adjusted the clock, leaving the other options as they were.
At the end it is a good idea to test the system and the cards through the [ System ] Test menu where you can select Load Test System functionality. Make sure all tests pass. Before I repaired my analyzer, a number of acquisition tests failed.
As I said, it is mandatory to connect the 16500C to the local area network. Otherwise you are bound to use floppies for file transfers.
You can select to use either the TP interface or the BNC interface. I went with TP since I haven't seen a BNC hub since the mid '90s. IP address and gateway are easy to set. But make sure you are using a static IP address as the 16500C does not know DHCP. I have added a MAC-IP filter into the routing table of my network router. Thus the analyzer always connects with the same IP. I let the file timeout setting to defaults and gave the analyzer an unique name so that it can be identified on the X-Window server. Firepit seems like a good name. The machine spits fire (heat) from the right side like an erupt volcano.
That's about it for the LAN configuration. It is easy to configure and it works seamlessly.
In addition you can check existing LAN connections and the machine will show either X-Window connections or FTP connections. Ethernet Statistics will show how many packets the LAN interface processed.
The built-in FTP server can be accessed using two different accounts.
To access the 16500C from the PC you have to use the analyzer IP address using the standard FTP port 21. Beware that your FTP client must not use multi-connection file transfers or the 16500C will freeze.
The 16500C mainframe can be accessed via NFS protocol. Since I have not found any way to make Windows talk NFS, I have not dug deeper into this connectivity method.
This is a bit more complicated than the rest of the 16500C configurations, especially if you want to use Windows instead of Unix or Linux. I am using Windows thus I will detail the way I managed to get the analyzer screen on my PC.
If you reached this step then you have succeeded to connect the 16500C mainframe to your X11 server on your PC. Honestly it took me a couple of days to figure out these steps. But I finally got it working. Unfortunately, the analyzer screen is fairly small at 576 x 369 px so it looks small if you have a high resolution computer screen.
Since this is an analysis system it means that additional analysis software can be installed on the hard disk drive. I am mainly interested in analyzing x86 architecture system design projects. Thus I find useful anything that is related to my scope. Let's see what software I can still find available.
I found the inverse assemblers for these old HP logic analyzers on the EEVblog on the HP Logic Analyzer Inverse Assemblers topic. The compressed file is called invasm_v3.zip and contains inverse assemblers for common processors such as Motorola 68k series, various x86 flavors, and Z80. There are also some other interesting files on that topic, including the source code for the inverse assemblers. I will do some research and investigations on these sources somewhere in the future.
I downloaded the compressed file to my computer and extracted what seemed of interest for my projects: the 80386 and Z80 inverse assemblers. I was a bit puzzled by the naming conventions on the inverse assemblers, but the author of that thread did a good job explaining them. I am not going to reprise his words here as they can easily be found by reading that forum thread.
Next I created a directory called INVASM on the 16500C hard disk drive and I used FTP to copy the inverse assembler files.
Of great interest are the configuration files for the logic analyzer. I believe that originally these files targeted the HP 16510 logic analyzer card. But as soon as I load one of these configuration files to an appropriate logic analyzer -- in my case it is LA in slot D -- the machine informs me on the correct mapping of the cables to the HP 10269C general purpose probe interface. This is a neat feature which I wasn't expecting at all. I was even prepared to do reverse engineering of the connections before being able to use the inverse assemblers.
It is interesting to note that loading a configuration file will also load the appropriate inverse assembler. At least so it appears. Anyway, another way to load the inverse assembler is to highlight the file and execute a load command into the appropriate logic analyzer.
Later Edit: By hazard, I have just stumbled across an HP document called State and Timing Analyzers for the HP 16500C Logic Analysis System where it is clearly stated that the 16500C mainframe will automatically convert configuration files from different logic analyzers to the 16555A/D logic analyzers. I am quoting directly from page 6 of the document itself.
The HP 16550-series automatically translates configuration files from the HP 16510A/B, 16511B, 16550A, 16540A/D, 16541A/D, 1650-series, 1660-series; and 1670-series logic analyzers.
Thus it is mystery solved for the configuration files conversion. Let's close the bracket and go back to the essay now.
Just to test that everything is correctly assigned, I opened the [1M Sample LA D] Format menu and we can see that the labels are all mapped to their specific signals on the logic analyzer PODs.
There are some other files in the archive.
That's it for now on installing the inverse assembler software.
The E2450A software package is available on the Keysight site under the form of a single compressed file. I downloaded the file and extracted its contents on my PC. Next I started an FTP client and copied the OPT5_032 file and the MESSAGES and OBJECTS directories to the SYSTEM directory on the 16500 hard disk drive. Then I power cycled the logic analysis mainframe for the changes to take effect.
The Symbol Software utility appears now on the [System] Configuration screen in both the Options widget and the System menu.
For the moment I don't have any .OMF files to test the Symbol Utility. This is another side project that I will investigate in the future.
In order to use the digital sampling oscilloscope (DSO) card, you first have to perform a full calibration. This is a lengthy process and only needs to be done once. The settings will be stored in the battery back-up non-volatile RAM that is present on the oscilloscope card itself.
The calibration is triggered from the Test System User Interface. In order to load it, you have to go to [ System ] Test menu where you can select Load Test System. In the Test System UI you need to select the digitizing oscilloscope card and then you can invoke the calibration routine which will take anywhere from five to ten minutes. It is a good idea to also run all the possible tests on the oscilloscope card to make sure it works accordingly.
Once all hardware peripherals are inserted in their respective sockets and all software modules are installed, the [ System ] Configuration screen appears like this.
All good for now, the unit is ready for use.
I think the best way to illustrate the operation of the 16500C unit is by taking a concrete example. What needs to be done is to configure one of the logic analyzers to the specifics of the device under test (DUT). Then it is up to the data acquisition phase. Once we have the data collected we can analyze it. That is what I am planning to describe in the following lines.
I thought a bit on what device to simulate for educational purposes. Initially I wanted to do a BCD to decimal converter but that would've implied a bit more glue logic to make it run properly. Then I came up with the idea of taking a CD4060 ripple counter IC and applying a square wave clock signal directly from my functions generator. This one IC and no extra parts circuit is actually the simplest example that I can think of. In addition I can easily build it on the prototyping board. I never liked prototyping boards for some reasons, but in this case it is actually the perfect tool at the perfect time in the perfect place.
The CD4060 integrated circuit implements a 14-stage ripple-carry binary counter and an internal oscillator. I am not that interested in the oscillator part so I will skip this for now. The counter circuitry is built using master-slave filp-flops with the outputs connected to the Q4-Q14 designated IC output pins. The clock signal accepts a maximum of 12 MHz frequency. I will use a 5 MHz clock source for the purpose of this example.
This is the circuit assembled on the prototyping board.
And here are the logic analyzer probes connected to the DUT. I am using POD1 of logic analyzer in slot A. Correctly connecting the probes is a painful operation and takes a lot of patience
Let's configure the machine now. From the System menu I selected the 1M Sample LA A option and I renamed the Analyzer 1 to CD4060. Depending on what type of analysis we want to run, we can select either Timing or State for the analyzer type. Let's go with State analysis.
In the Format 1 menu I renamed the Lab1 as OUTPUT and assigned the 10 necessary probe signals. Lab2 was renamed to CLOCK and the J signal was assigned to the clock input line of the CD4060 integrated circuit.
Then I saved the configuration of the logic analyzer in slot A to the internal storage for future references.
Now let's come back to the analysis. In the [1M Sample LA A] Waveform 1 menu I configured the system to only display waveforms for OUTPUT0-OUTPUT9 and CLOCK signals.
There is a special GRAPHICS directory that cannot be deleted. It always contains screenshots or the current screen you see on the 9" CRT screen. There are .PCX and .TIF color screenshots as well as .EPI and .TIF black and white versions of the same screen. I don't know what these are for but I can imagine that they are useful for debugging purposes. These files are always overwritten when you change screens.
This was quite an adventure and a lot of new stuff to learn in a short time. Documenting this journey definitely helped me to better sediment the knowledge I acquired on the 16500C logic analysis system. I hope you found this essay useful.
This essay is provided as-is and is not for commercial purposes. It reflects my experiments and research and should be treated as such. I release my work to the public for educational purposes. I did all this on my expense and in my free time. So if you like my work, or find it useful or inspiring for your projects, please consider a donation.
Copyright © 2004- Alexandru Groza
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