I decided to build an ISA video card after all. Since I already have a good video card, I know I had my fair share of doubts about the usefulness of such a project -- read the synopsis of ISA Audio Interface. But I wanted to learn about ISA video cards. And especially video graphics array (VGA) cards with basic graphics acceleration. I settled on the Tseng Labs ET4000/W32i video controller chip. There is plenty of documentation on the Internet and the Tseng Labs datasheets are insanely full of details. All this makes for another easy system design project. Well, I think designing this card was the easiest job of all I did so far in this domain. It took me about two weeks to read the various datasheets of the parts involved, around four days to draw the schematic and only a couple of days to completely hand-route all PCB tracks. By all means, that was fast!

I also inspected a lot of VGA ISA cards so that I learn as much as possible about the choice of components, PCB layout, and the like. I particularly enjoyed doing this, especially since I discovered this great site called VGA Museum where I could find cards that I didn't ever thought existed -- check this one for instance: Foundation Logic Ruby VGA. And I saw a lot of ISA hardware over the years. Well done on preserving the video card history and maintaining the site!

Here are the hardware specifications.

  • Very Fast MS-DOS Data Transfer
  • Good VGA Compatibility
  • Microsoft Windows Graphics Acceleration
  • True Color RAMDAC
  • 2 Mb RAM (Interleaved Mode)
  • Minimal Glue Logic
  • Individual hardware configuration switches and jumpers for all functions
  • 16-bit ISA-class printed circuit board construction

This video display controller ISA card contains only twelve chips. The main issue with these chips is that only the octal bus transceivers and 3-state buffers are available at Mouser. All the rest needs to be sourced from 3rd party sellers. I had some luck finding the ET4000/W32i graphics controller chip at a good price at a seller in China. The price was so good that I bought four chips. Unfortunately, the transportation fee was unexpectedly high. The FPM DRAM chips were pretty cheap and readily available at multiple parts sellers. The dual PLL clock generator circuit was harder to find but it turned out to be pretty cheap. Then again I had to pay for the transport. The true color RAMDAC and the UV-erasable EPROM are readily available on eBay. So, even if there are very few chips on this PCB, their combined price tag is not something to overlook.

The trigger to launch into such a project was when I accidentally found the ISSI IS41C16257-35T FPM DRAM chips. Seeing they have independent /CAS signals for both high and low byte signifies that I can use one 256Kx16 chip to store two bytes of video data in interleaved mode. This considerably reduces the number of memory chips to only four while providing nearly 64-bit memory access performance. The ET4000/W32i datasheet specifies memory speeds of 50 ns or better. The ISSI chips are rated 35 ns, which is perfect. Giving credit to the section that describes the memory controller in the ET4000/W32i datasheet, I am expecting slightly faster memory access times.

Next, I started imagining what the PCB would look like and then there was only a small gap before I began hunting for chips at various electronic parts sellers. This is my first computer hardware project that even received a non-cryptic name. I call this video card EXCELGRAPH.

Let's proceed.

Disclaimer: I reserve the right to change the schematic diagram, the PCB layout, or the implementation without further notice. This is an entirely hobby do-it-yourself design and I am not responsible for any damage made by any possible mistake in any version or revision of the schematic diagrams or PCB layouts. Since it is an advanced microelectronics project, it requires very good assembly and debugging skills. In addition, I cannot offer any further technical support other than the contents of this article.

This project is in its final stage.
Current iteration of ASSY. 2486-VDC-201 is VER. 1.3 REV. E

* * *

Laudatur ab his, culpatur ab illis. This project is provided as-is and is not for commercial purposes. It reflects my experimental work in microcomputer system design and should be treated as such. I release the schematic diagram and circuit board layouts to the public for educational purposes. I did all this at my own expense and in my free time. If you like my work, please consider making a donation. It helps me continue these kind of projects.

Schematic Diagram (VER. 1.3 REV. E)

Fig. 1: Electrical Schematic Diagram

Printed Circuit Boards

Fig. 2: Top Silkscreen

Fig. 3: Bottom Silkscreen

Fig. 4: Top Layer Printed Circuit Board

Fig. 5: Inner Bottom Layer Printed Circuit Board

Fig. 6: Inner Top Layer Printed Circuit Board

Fig. 7: Bottom Layer Printed Circuit Board

Fig. 8: Top Layer Printed Circuit Board - Simulation

Fig. 9: Bottom Layer Printed Circuit Board - Simulation

If you want to see or hide older schematic diagrams please use the following function: Show Older Schematic Diagrams

Gerber Files

Here are the Gerber files compressed in a .ZIP archive.
Please note that the file naming convention that I used is what OSHPark normally expects.
You can also order the printed circuit board directly from OSHPark by following the link in the bill of materials below.

Compressed Gerber Files:

Bill of Materials (BOM)

The following list contains the parts that are required to assemble this ISA video display controller card.

IdentifierValueQtyNotesMouser Number
Printed Circuit BoardASSY. 2486-VDC-2011VER. 1.3 REV. EOrder from OSHPark
IC1, IC274F2452Octal Bus Transceiver595-SN74F245N
IC3, IC474F2442Octal 3-state Buffer595-SN74F244N
IC5Chrontel CH9294E1Dual Clock GeneratorOrder from 3rd Parties
IC627C256-101UV-erasable EPROMOrder from 3rd Parties
IC7Tseng Labs ET4000/W32i1Video ControllerOrder from 3rd Parties
IC8-IC11ISSI IS41C16257-35T4256Kx16 FPM DRAMOrder from 3rd Parties
IC12AT&T ATT20C4901True Color RAMDACOrder from 3rd Parties
D1-D61N41486Small Signal Diode78-1N4148
D7LM3851Voltage Reference Diode926-LM385BZ-12/NOPB
C1-C16, C21-C24, C27-C29100 nF / 50 V23MLCC80-C322C104M5R-TR
C17-C20, C5010 nF / 50 V5MLCC80-C315C103J5R
C25, C26, C36-C4910 uF / 25 V16Tantalum Capacitor80-T350E106M025AT
C302.2 uF / 25 V1Tantalum Capacitor80-T350B225K025AT
C31-C33100 pF / 50 V3MLCC80-C320C101J5G
C34-C35120 pF / 50 V2MLCC80-C315C121J5G
C5147 pF / 50 V1MLCC80-C315C470J5G
R1-R3150 Ω3Metal Film Resistor71-RN55C1500B
R4, R533 Ω2Metal Film Resistor71-RN55C33R0F
R6147 Ω1Metal Film Resistor71-RN55C-B-147/R
R71 kΩ1Metal Film Resistor71-RN55E-B-1K/R
R8, R1010 kΩ2Carbon Resistor588-OK1035E-R52
R9220 Ω1Carbon Resistor588-OK2215E-R52
R11, R121 kΩ2Carbon Resistor588-OK1025E-R52
R135.6 kΩ1Carbon Resistor588-OK5625E-R52
R142.2 kΩ1Carbon Resistor588-OK2225E-R52
R15330 Ω1Carbon Resistor588-OK3315E-R52
R164.7 kΩ1Carbon Resistor588-OK4725E-R52
R17, R18470 Ω2Carbon Resistor588-OK4715E-R52
RA14 x 2.2 kΩ1Resistor Array652-4608X-2LF-2.2K
RA2, RA35 x 270 Ω2Resistor Array652-4610X-2LF-270
L1-L5133 Ω / 100 MHz5Ferrite Bead623-2743002111
L6-L868 Ω / 100 MHz3Ferrite Bead623-2743001111
X114.31818 MHz1Quartz Crystal695-HC49US-143-U
IC Socket20-pin5IC1-IC5575-193320
IC Socket28-pin1IC26575-11043628
IC Socket44-pin PLCC1IC12575-944424
JP1, JP22-pin Header2Jumper649-68001-202HLF
J72-pin Header1Header649-68001-202HLF
J115-pin Connector1Female D-Sub617-09-56-152-5612
ScrewScrewlock 4-40 UNC2For J1617-09670019941

Alternatively you can use the following link to the Mouser project that I created for this ISA card. It should make ordering of parts and removing typing faults pretty easy.


Lately I have observed that Mouser discontinued some of the parts in the list above. If you decide to build this project, then you need to find alternatives. It is out of my scope to maintain the correctness of the parts list above.

The following list contains the parts that are required to assemble the video DRAM refresh drivers. The parts have to be ordered twice.
These are required to fix stability issues only of video card ASSY. 2486-VDC-201 VER. 1.3 REV. D/E.

IdentifierValueQtyNotesMouser Number
Printed Circuit BoardASSY. 2486-DRD-9031VER. 1.0 REV. COrder from OSHPark
IC174AHCT3671Hex Line Driver595-SN74AHCT367D
C1100 nF / 50 V1MLCC80-C0805C104K5RACLR
C1, C21 uF / 35 V2Tantalum Capacitor80-T491A105M035AT
PinPress-fit Terminal Pin12Interface575-0542000150000

Alternatively you can use the following link to the Mouser project that I created for the DRAM refresh driver board. It should make ordering of parts and removing typing faults pretty easy.


Assembly Instructions and Notes

Here is a list of things you need to pay attention to should you decide to build such ISA video display controller card.

  • Inspect the printed circuit board once you receive it. Normally OSHPark produces very good quality boards but one never knows. There must be absolutely no short circuits on the printed tracks. If the PCB is faulty then it can damage other ISA cards that you might install in the system.
  • Carefully observe polarity of the tantalum electrolytic capacitors on the silkscreen. I made sure there is no error on the printout. Tantalum capacitors will violently explode and burst in fire if mounted in reverse, possibly injuring you.
  • Take your time to solder all the components on the board. There are a lot of solder points and if you don't have patience in general, then this project might not be for you.
  • Use a temperature-controlled soldering station and quality solder. Take care not to leave solder bridges as any short circuit will most likely lead to failures.
  • In order to ease-up the PCB assembly, I would suggest mounting parts in the following order: Tseng Labs ET4000/W32i, ISSI IS41C16257-35T chips, diodes, carbon resistors, metal film resistors, quartz crystal, IC sockets, resistor networks, MLCC capacitors, tantalum capacitors, jumpers, ferrite beads, connectors.
  • At the end, clean any flux residues with isopropyl alcohol.

Principle of Operation

The schematic is very explicit, so I don't consider a block diagram really necessary. But I will provide some details that I gathered from the datasheets on the main chips that make up this video display controller card.

The video display controller is controlled by the Tseng Labs ET4000/W32i video controller integrated circuit. This chip has the following features.

  • 8-bit, 16-bit, or 32-bit Memory and I/O Bus
  • 20-bit, 22-bit, or 24-bit Address Bus
  • Supports ISA, EISA, MCA, or Local Bus
  • Interlaced or Non-interlaced VSYNC and HSYNC with Polarity Control
  • External RAMDAC Lookup (Pixel Clock, Blanking, R/W Control)
  • 8-bit Pixel Output RAMDAC Interface
  • VGA Compatible Data Rotate/Mask/Logical Functions
  • Proprietary Enhanced-LRU Replacement Policy and Block Transfer Cache System
  • Up to Two FIFOs for Display Pixel Data
  • 512 Kb, 1 Mb, 2 Mb, 4 Mb linear, or 2 Mb Interleaved FPM DRAM
  • System Priority Controller Resolves Multiprocessors and Resource Requests
  • Horizontal CRT Controller with 9-bit Programmable Display Enable, Blanking, and HSYNC
  • Vertical CRT Controller with 11-bit Programmable Line Counter for Display Enable, Blanking, Split Screen, and VSYNC
  • 20-bit Linear Doubleword Address Generator with Programmable Starting Address and Row Address Offset
  • 5-bit Row Scan Address that Provides up to 32-line Character Height
  • 64 x 64 x 2 Sprite Creates a Second Hardware Window for Simultaneous Display of Graphics or 30 fps Digital Video
  • 20-bit Cursor Position and 5-bit Cursor Start, 5-bit Cursor End Control
  • Support for up to Two 256 Character Sets
  • IBM-compatible Text Attribute Decoding and Cursor Blink/Underline
  • AT&T-compatible Underline Decoding in Color Text Mode
  • 6, 7, 8, 9, 10, 12, and 16 Pixel Programmable Text Font Width
  • Up to Eight Pixel Clock: 86 MHz (Graphics Mode), 56 MHz (Text Mode), 50 MHz (System Clock)
  • Graphics Accelerator Supports 32-bit with 256 Raster Operation and D/S/P BLT, Tiling, Pattern, FG/BGROP, and CPU-assisted Operations
  • Linear Word Graphics and VGA-compatible Text Foramt up to 16-bit Wide Character
  • 1024 x 768 px in 65K Colors Interlaced or Non-interlaced in Graphics Mode
  • CGA/MDA/HERC/EGA/VGA Register Level Compatibility
  • 8514A Display Level Compatibility
  • Zero Wait State Operation
  • Programmable /CAS before /RAS Refresh Provides DRAM Refresh During Display Blanking

The VGA analog signal interface is made possible by the AT&T ATT20C490-80 RAMDAC chip. It has the following features.

  • 256, 32K, 64K, 256K, and 16M On-Screen Colors
  • 24-bit, 16-bit, 15-bit True Color, 8-bit Pseudo Color
  • Aliasing and Window Color Corruption is Eliminated in True Color Mode
  • XGA, TARGA, and HICOLOR Formats
  • VGA Accessible Control Register
  • Antisparkle Circuitry
  • 256 x 24 Color RAM
  • 15 x 24 Overlay RAM
  • 1280 x 1024 px / 60 Hz Non-interlaced Maximum Resolution
  • 1024 x 768 px / 85 Hz Non-interlaced Maximum Resolution

The master (video) and system (memory) clock signals are generated by the Chrontel CH9294E dual PLL frequency synthesizer integrated circuit. It has the following features.

  • Supports VGA, SVGA, XGA, and 8514A Graphics Standards
  • Generates 16 Video Clock Frequencies
  • Generates 4 Memory Clock Frequencies
  • Supports Output Frequencies up to 135 MHz
  • Requires a Single 14.31818 MHz Quartz Crystal

I thought early '90s video display technology was more or less a bad joke and everything was spartan and simple. Well, after reading through the ET4000/W32i datasheet, my preconceptions were drastically destroyed. Good for me as I learned that things were actually very advanced and complicated. After all this was cutting edge technology back in 1993. In the same way NVIDIA RTX3090 GPU is at the end of 2020. I think this is a good analogy.

Interface Connectors Description

The following section describes all the interface connectors and their respective pinouts.

J1VGAVGA Output1 - RED
3 - BLUE
4 - Monitor ID2
5 - Ground (HSYNC)
6 - Ground (RED)
7 - Ground (GREEN)
8 - Ground (BLUE)
9 - NC
10 - Ground (VSYNC)
11 - Monitor ID0
12 - Monitor ID1
13 - HSYNC
14 - VSYNC
15 - Monitor ID3

ISA Card Configuration

I have provided some basic card configuration options under the form of jumpers.
The star (*) symbol signifies the default option.

JP10WSZero Wait StateCL: Enabled (*)
OP: Disabled
JP2IRQ9Vertical Retrace IRQCL: Enabled
OP: Disabled (*)

Construction and Pictures

The PCBs have arrived from the factory. Now on to the assembly procedure.

This is the bare 4-layer PCB, component side.

And the solder side.


More details.

I have soldered one memory chip and the video controller chip.

Details on the soldering job.

All memory chips are in place.

Small-signal diodes and almost all of the metal film and carbon resistors are the first non-SMD parts that I soldered next.

Other parts such as quartz crystal, ferrite beads, and MLCCs follow next.

Tantalum capacitors and integrated circuit sockets are soldered as well.

Then, I inserted all the logic ICs into their specific sockets. I programmed the ROM with the modified BIOS that I described in the VGA ROM Fonts essay.

Conclusions and Reflections

My enthusiasm quickly turned down when I first tested the card. The PC booted but the colors were very, very weird. Some sort of weird negative colors with a strong emphasis on green. There were also a lot of vertical stripes and weird video artifacts in graphics mode and bad character rendering in text modes. Time for investigation and debugging. Let's walk through the following list.

  1. Measuring the voltages across the ICs on the PCB revealed a steady 4.98 V. All good.
  2. I measured the clock generator circuit outputs and the clock carrying lines were very clean. Furthermore, these clock signals propagate correctly on the PCB. Pixel clock signal is good as well. Nothing to do here.
  3. Measuring the red, green, and blue signals on the RAMDAC revealed some weird activity on the oscilloscope screen. Thus, I have to investigate a bit the RAMDAC interface and PCB connections.
  4. The vertical lines are most probably related to the DRAM interface. So I have to investigate that as well.

Let's just skip the first two points and concentrate on the other ones.

RAMDAC Interface

As I said, while probing the VGA output signals with the oscilloscope, I found some strange activity. Some of the color signal pulses were actually inverted. It took me less than two seconds from the moment I saw the scope screen to the identification of the issue. It was pretty much clear that I somehow mis-connected the RAMDAC.

I inspected the schematic diagram but there was nothing wrong. Then one thought crossed my mind. Have I done something wrong when I designed the RAMDAC part library? Yes I did. I inverted all data and all video data pins. I corrected my library right away.

I just wasted an hour or so to build a simple adapter just to prove that my design works correctly. It looks very messy indeed.

Since I already have three quasi-working VER. 1.3 REV. D PCBs, I designed a small RAMDAC adapter PCB so that I don't have to throw these PCBs away. In the meantime, the RAMDAC adapter PCB arrived in the mail. Here it is.


Then I soldered this adapter on the graphics card PCB. I'd say it looks nice. Unfortunately, I lifted one of the fragile pads on the solder side. The result is that one of the RAMDAC pins cannot connect to it's appropriate signal on the main PCB. A quick and dirty wiring job solves the issue.

One issue solved. Now let's attack the next one.

DRAM Interface

Although I initially made some impedance calculations for the main high-speed transport lines, somehow the reality proved me wrong. I decided to do some spartan experiments with the impedance matching resistor arrays and I have observed improvements with each step of increasing the resistance.

So I incrementally increased RA2 and RA3 until I got rid of all visual artifacts. I experimentally found that a 300 Ω resistor array would be the best. But I had difficulties sourcing such parts. Thus, I went with 270 Ω resistor arrays which allow a good impedance matching delay line effect for the required /RAS and /CAS high-speed signal transport line timings.

If, for some reason, there are still visual artifacts issues, then a solution would be to further increase RA2 and RA3 to 330 Ω. Further investigation revealed that the artifacts are caused by a timing issue between the DRAM controller inside the ET4000/W32i chip and the ISSI DRAM chips. The solution would be to introduce an artificial propagation delay of about 4 ns. The hack of using 270 Ω resistors acts like a delay line for the memories, thus making the DRAM timing acceptable. However, it is a hack nonetheless. So I will update the design. In my case, I find the card stable in 99 % of all normal usecases. A few MS-DOS games still show artifacts in certain screens (most notably on High Score screens). But that does not bother me at all.

The new resistors are soldered in place.

Another issue temporarily solved.

Recently, I left a comment on a retrocomputer enthusiast forum, describing these artifacts. I will paste it here as well.

Video DRAM (and other DRAM as well) chips have /RAS and /CAS lines that are used to constantly refresh the contents of the memory cells. The tracks between the memory controller and the individual memory chips act like high-speed transmission lines. Furthermore, memory chips row and column strobe signals can be connected in parallel (such as the case of EXCELGRAPH and many other designs). DRAM chips have a specific capacitive loading rating so you somehow need to calculate and take into consideration the distributed capacitance and inductance of that transmission line.

Long story short, using dampening series resistors will reduce undershoot (viewable on a high-speed oscilloscope screen) of the /RAS and /CAS signals. The resistors will also minimize signal reflections and will improve overall stability of the DRAM system.

Now the fact is that these dampening resistors should be between 10 Ω to 33 Ω or whatever small value results from the calculus.
Apparently, the ISSI memories that I used don't like values that small. And I haven't investigated why, yet. I do have a high-speed 500 MHz bandwidth oscilloscope but I wasn't really interested in what was happening there. Once I experimentally found out that increasing these values by a 10th order and seeing everything works fine, I lost interest in troubleshooting the initial design (where I used 33 Ω resistors).

The artifacts are described as merely entire groups of pixel data that gets corrupted. The CRT screen will either ignite these pixels all white or they will have random colors based on the corrupted memory data.
Once I increased the dampening resistors to about 60 Ω, the artifacts were present only on repetitive vertical lines of the CRT screen.
Going even further to about 150 Ω, the artifacts were reduced drastically and appeared only in certain cases, with games that had weird timings or weird video RAM control techniques.

Take this video, for instance at time 2.25 when the DOOM demo begins, the CRT randomly ignites yellow pixels. In fact, they are not that randomly ignited. They are part of the memory bank controlled by /CAS2, /CAS3, /CAS6, /CAS7, and /RASB signals and they appear on individual parallel vertical lines on the CRT -- even though that is not visible at first glance.

There are some other games, such as Duke Nukem 2 or Commander Keen (all series) that present weird faulty pixels but only in the High Scores and the Main Menu screens.
Otherwise, they're good to go.

Even though the datasheet specifies DRAM speeds of 50 ns or better, in the end, I believe the ET4000/W32i controller was not meant to be used with DRAM chips that fast (35 ns). Or I overlooked the ISSI datasheet (honestly I haven't inspected the timing diagrams anyway, I was mainly interested in the physical connections and if I am able to drastically reduce chip count to still have 2 Mb of memory in interleave mode).

I just thought this might be an interesting read in this context.


I have updated resistors R17 and R18 to 470 Ω.

Video Tests

I ran a suite of tests provided by the VDIAG.EXE program by Tseng Laboratories, Inc.

Everything went well. Here are some pictures with the CRT screen. I took the pictures with my mobile phone so beware of the moire effect.

Final Conclusions

I am happy the idea of an adapter crossed my mind. So far, all is not lost. I will still be able to use the PCBs I already have. In a way, the small adapter looks very nice by itself. When mounted on the PCB assembly, it looks even more technical. It reminds me of limited production laboratory equipment PCBs. I've seen some very nice PCBs for physics experiments with some very ingenious PCB post-production corrections with all kind of adapters.

Here is the final VER. 1.3 REV. D video card.

The connection wire to the RAMDAC adapter looks very steampunk. It is a prototype. So weird looks are accepted!

EXCELGRAPH is a good name for an ISA video card that can handle all MS-DOS games and most of the Windows games up until the year 1998 or so. Well, the FPS of the Windows 3D games is suffering a lot due to the low ISA bus bandwidth. But then again, the Windows 98 era goes hand in hand with PCI graphics cards.

But hey, I just proved that an all ISA system consisting entirely of DIY cards can be used to play StarCraft fluently. Don't believe me? Check this video on YouTube. It clearly shows how the ISA bus can handle four storage devices, one sound card, one video card, and an Ethernet card and still deliver performance. I am positively sure the ISA bus was not meant for this kind of system. Then again, it is fun to push the limits of computing hardware.

Most probably, I will not produce the VER. 1.3 REV. E PCB for personal use. But I updated the schematic and the Gerber files so if you would venture into building such a video card, you will not have to mess around with any adapter.

I did some slight updates to the ROM BIOS. I injected my own assembly routine that displays and highlights the card name.

The modified ROM is for personal use only. It will not be available for download. But you can find compatible ROM BIOS binary images on the Internet.

Constructing a Second Video Display Controller

I wanted to experiment a bit with this graphics card design and improve the memory driver to ensure bulletproof operation and also easier replication by hobbyists. Since the first card that I built is in use in one of my vintage computers, I cannot conduct any experiments on it. Thus, I have to build another one. And since I still have the original VER. 1.3 REV. D PCBs and the RAMDAC adapters, I quickly decided to build a test subject.

The first thing to do is to solder the RAMDAC on the interposer PCB. When you need to protect sensitive areas from heat and flux or solder, Kapton tape is your friend. It also ensures good mechanical fixation to the workbench.

I used the same technique to solder the interposer to the main PCB. First, I applied flux on each SMD pad on the interposer. Then I carefully positioned the adapter on the main PCB and secured it with Kapton tape. Next, I flipped the main PCB and applied flux to each through hole soldering pad. The final step was to fill each hole with solder. Thus, I managed to create a spartan ball grid array (BGA) soldering technique without using additional individual interconnect pins.

All SMD devices are soldered already.

Detailed view on the dynamic RAM chips.

RAMDAC adapter interposer printed circuit board looks really good.

And a view from another side. Apparently, I have aligned the BGA interposer PCB with great precision without expensive X-ray equipment.

Solder side for the RAMDAC adapter.

Advancing with soldering of the passive components.

Details on the various small passive parts in the analog VGA signal section. Even though this is just another prototype, and a test subject after all, it doesn't mean it shouldn't look good!

I installed precision extension sockets in place of the old dampening resistor arrays. The new memory drivers will be interfaced through these sockets as follows.

  • one driver for memory bank A
  • one identical driver for memory bank B

Improving the Memory Refresh Driver

As previously said, I have replaced RA2, RA3, C13, and C15 with augat sockets. This would allow me to experiment a bit with the dynamic memory refresh driver section. From the initial prototype I have learned that the various /CAS and /RAS signals require a slight delay in order to trigger correct DRAM refresh. My initial hack was to use larger resistor arrays to introduce this delay. But now I am going to experiment with an active memory driver IC.

Once I come up with a working design, I plan to make two small interposer PCBs, each carrying an improved memory driver circuit. These adapters will draw power from the former C13 and C15 decoupling capacitor pins and will use the existing RA2 and RA3 terminals for the refresh signals transmission.

I connected the logic analyzer to the improved memory driver test circuit.

Versions and Revisions

This section lists the project version and revision history.

VER. 1.3 REV. E

  • Corrected RAMDAC component layout
  • Increased memory /RAS and /CAS signal tracks width
  • Corrected Chrontel CH9294 IC identifier
  • Small updates to component values
  • As before, it works OK with 270 Ω dampening resistors, but the improved RAM drivers are still required for best operation

VER. 1.3 REV. D

  • Fully functional (with RAMDAC adapter) initial prototype version
  • Works OK with 270 Ω dampening resistors, but the improved RAM drivers are required for best operation

Copyright © 2004- Alexandru Groza
All rights reserved.
VER. 1.0 | REV. A